Arm Quick Reference

© Timothy Roddis

ARM Instruction Formats
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
Conditional				0	0	I	Opcode				S	Rn				Rd				Operand 2												ALU
Conditional				0	0	0	0	0	0	A	S	Rd				Rn				Rs				1	0	0	1	Rm				Multiply
Conditional				0	0	0	1	0	B	0	0	Rs				Rd				0	0	0	0	1	0	0	1	Rm				Swap
Conditional				0	0	0	1	0	PS	0	0	1	1	1	1	Rd				0	0	0	0	0	0	0	0	0	0	0	0	MRS
Conditional				0	0	0	1	0	PS	1	0	1	0	0	1	1	1	1	1	0	0	0	0	0	0	0	0	Rm				MSR(all)
Conditional				0	0	I	1	0	PS	1	0	1	0	0	1	1	1	1	1	Source Operand												MSR(flag)
Conditional				0	1	I	Pr	U	B	W	LS	Rn				Rd				Offset												LDR/STR
Conditional				0	1	1	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	X	1	X	X	X	X	Undefined
Conditional				1	0	0	Pr	U	S	W	LS	Rn				Registers (R15-R0)																LDM/STM
Conditional				1	0	1	Ln	Offset																								Branch
Co-processor instructions
Conditional				1	1	0	Pr	U	N	W	LS	Rn				CRd				CP#				Offset								Transfer
Conditional				1	1	1	0	CP Op				CRn				CRd				CP#				CP			0	CRm				Op
Conditional				1	1	1	0	CP Op			LS	CRn				CRd				CP#				CP			1	CRm				RTransfer
Conditional				1	1	1	1	Ignored By ARM																								SWI
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00

Bit fields
A	Accumulate - multiply and accumulate
B	Byte/Word bit - set for byte transfer
I	Immediate flag
Ln	Link bit for branches - set for link
LS	Load/Store bit - set for Load

Bit fields
Pr	Pre/Post incrementing bit - set for pre
PS	SR selection bit - set for SPSR_, clear for CPSR
S	Set condition flags - PSR bits modified or force user mode if set
U	Up/Down bit - set for increment, clear for decrement
W	Write back bit - set for write back into base register

Condition Codes
0000	EQ	Equal	Z	Z=1
0001	NE	Not Equal	¬Z	Z=0
0010	CS	Carry Set	C	C=1
0011	NE	Carry Clear	¬C	C=0
0100	MI	MInus	N	N=1
0101	PL	PLus	¬N	N=0
0110	VS	oVerflow Set	V	V=1
0111	VC	oVerflow Clear	¬V	V=0

Condition Codes
1000	HI	HIgher	C & ¬Z	C=1 and Z=0
1001	LS	Lower or Same	¬C \| ¬Z	C=0 or Z=1
1010	GE	Greater or Equal	¬(N ^ V)	N=V
1011	LT	Less Than	N ^ V	N<>V
1100	GT	Greater Than	¬Z & ¬(N ^ V)	Z=0 and N=V
1101	LE	Less or Equal	Z \| (N ^ V)	Z=1 or N<>V
1110	AL	ALways	TRUE
1111	NV	NeVer	FALSE

NB: HS (Higher or Same) and LO (LOwer) are synonyms of CS and CC respectively

ALU Operations Codes
0000	AND	Rd	=	Rn	AND	Op2					Logical ops: V unaffected C last bit shifted out Z if zero N bit 31
0001	EOR	Rd	=	Rn	EOR	Op2
0010	SUB	Rd	=	Rn	-	Op2
0011	RSB	Rd	=	Op2	-	Rn
0100	ADD	Rd	=	Rn	+	Op2
0101	ADC	Rd	=	Rn	+	Op2	+	C
0110	SBC	Rd	=	Rn	-	Op2	+	C	-	1
0111	RSC	Rd	=	Op2	-	Rn	+	C	-	1
1000	TST			Rn	AND	Op2					Arithmetic ops: V signed overflow C (addition) carry out of bit 31 C (subtraction) NOT borrow Z result is zero N bit 31
1001	TEQ			Rn	EOR	Op2
1010	CMP			Rn	-	Op2
1011	CMN			Rn	+	Op2
1100	ORR	Rd	=	Rn	OR	Op2
1101	MOV	Rd	=	Op2
1110	BIC	Rd	=	Rn	AND	¬Op2
1111	MVN	Rd	=	¬Op2

In ALU Ops
Operand 2
11	10	09	08	07	06	05	04	03	02	01	00
Shift								Rm				I = 0
Rotate				Immediate								I = 1

In LDR & STR
Offset
11	10	09	08	07	06	05	04	03	02	01	00
Immediate												I = 0
Shift								Rm				I = 1

In MSR(flags)
Source operand
11	10	09	08	07	06	05	04	03	02	01	00
0	0	0	0	0	0	0	0	Rm				I = 0
Rotate				Immediate								I = 1

Shifts
Shift field
11	10	09	08	07	06	05	04
Rs				0	Type		0	Bottom byte of Rs specifies shift amount
Shift amount					Type		1	Shift amount is a 5-bit unsigned integer

Type
00	logical left
00	logical right
00	arithmetic right
00	rotate right

Registers
26-bit PC and PSRs
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
N	Z	C	V	I	F	Program Counter																								Mode		26-bit
N	Z	C	V																					I	F		Mode					xPSR

Processor Modes
M4	M3	M2	M1	M0	Mode
0	0	0	0	0	User26
0	0	0	0	1	FIQ26
0	0	0	1	0	IRQ26
0	0	0	1	1	SVC26
0	0	0	0	0	User
0	0	0	0	1	FIQ
0	0	0	1	0	IRQ
0	0	0	1	1	SVC
0	0	1	0	0	ABT
0	0	1	0	1	UND