The TMS1000 is actually a series of 4-bit microprocessors produced by Texas Instruments. The units are actally microcontrollers containing ROM, RAM, I/O, & CPU on one chip. The following table summarizes the differences between the units.
|Pkg Pin Count||28||40||28||40||28||40|
|ROM Program Bytes||1024||1024||1024||1024||2048||2048|
|RAM Data Nibble||64||64||64||64||128||128|
|R Signal Outputs||11||13||11||13||11||16|
|O Data Outputs||8||8||8||10||8||8|
The block diagram of the cpu (inside the dotted line).
With the TMS1000 series, what you see is all you get. The units are not capable of expansion in any way. The highest clock frequency attainable by the series is 0.4MHz. this results in a 2.5 microsecond clock cycle. All instructions execute in 6 clock cycles. The devices were fabricated using PMOS and required a single -15V supply.
NOTE: The X register is two bits wide on the devices with 64 nibbles of RAM and three bits wide on the 128 nibble RAM units. The accumulator is standard type, aside from being four bits wide. The concatenated X and Y registers become a six or seven bit data register. This creates a pointer into the 64 or 128 nibbles of RAM. The concatenated Page Address Register and Program Counter constitute a ten bit program counter. On the devices with 2048 bytes of program memory, there is a 1 bit "Chapter Flag" used as the most significant bit of an eleven bit program counter. The Y register can also be used as a secondary accumulator and an output address register. The Subroutine Return Register and Page Buffer Register are storage areas that implement a one level subroutine call mechanism. When a subroutine is called, the contents of the Page Address Register and the Page Buffer Register are swapped. The Program Counter is copied to the Subroutine Return Register. The subroutine target address is then moved to the Program Counter.
Note that The R and O outputs are resposible for the additional pins on the 1200,1270, and 1300 chips. All of these units have internal clock logic which can be connected to an RC circuit with one end of the capacitor connected to Vss, one end of the resistor connected to Vdd and the opposite ends of the components connected to both OSC1 and OSC2. If an externally generated signal is to be used, it must be connected to OSC1 while OSC2 is grounded. A design utilizing many clocked chips would benefit from this setup.
The INIT (reset signal) should be held high for at least 6 clock cycles after power is applied. Reset causes the Page Address and Page Buffer registers to be loaded with binary ones. The O and R outputs as well as the program counter are zeroed. A consequence of this is that upon reset, the first instruction executed is at hex location 3C0.