Fairchild Semiconductor F8

Introduction

NOTES: The folowing symbols are used in this table: When the "machine cycle" column contains two numbers, the first is if the branch is not taken the other number is if it is.

Also, the table immediately following shows flags affected by instructions. I forgot to add it to the "main" table.  An X indicates the instruction modifies the the flag. A zero or one indicates the flag is set or reset when this instruction is executed.
Fairchild F8 instruction set flag status list
Fairchild F8 instruction set flag status list
Mnemonic Flags
C Z S O
AS r X X X X
ASD r X X X X
NS r 0 X X 0
XS r 0 X X 0
DS r X X X X
AM X X X X
AMD X X X X
NM 0 X X 0
OM 0 X X 0
XM 0 X X 0
CM X X X X
AI DATA8 X X X X
NI DATA8 0 X X 0
OI DATA8 0 X X 0
XI DATA8 0 X X 0
CI DATA8 X X X X
ADC 0 X 1 0
SR 4 0 X 1 0
SL 1 0 X X 0
SL 4 0 X X 0
COM 0 X X 0
LNK X X X X
INC X X X X

Fairchild F8 opcode detail
Fairchild F8 opcode/mnemonic detail
Mnemonic Operand Machine
cycles		 Operation Op Code
 
F8 I/O opcodes
INS P4 4   Input to Accumulator from I/O port 1010eeee  
IN P8 2   Input to Accumulator from I/O port 26 SS
OUTS P4 4   Output to I/O port from Accumulator 1011eeee  
OUT P8 4   Output to I/O port from Accumulator 27 SS
F8 Primary memory reference opcodes
LM   2.5   Load Accumulator via DC0 and auto-increment DC0 16  
ST   2.5   Store Accumulator via DC0 and auto-increment DC0 17  
LR A,r 1   Load the contents of the specified register SR into Accumulator. increment or decrement ISAR if specified by r 0100aaaa  
LR A,DPCHR 1   Load Accumulator with the contents of the specified DPCHR 000000cc  
LR r,A 1   Load the contents of the Accumulator into the specified register. increment or decrement ISAR if specified by r 0101aaaa  
LR DPCHR,A 1   Load contents of Accumulator into the specified DPCHR 000001cc  
LR H,DC0 4   Load contents of Scratchpad registers 10 and 11 into DC0 11  
LR Q,DC0 4   Load contents of Scratchpad registers 14 and 15 into DC0 0E  
LR DC0,H 4   Load contents of DC0 into Scratchpad registers 10 and 11 10  
LR DC0,Q 4   Load contents of DC0 into Scratchpad registers 14 and 15 0F  
LR K,PC1 4   Load contents of Register K into the Stack register 08  
LR PC1,K 4   Load contents of the Stack register into Register K 09  
LR PC0,Q 4   Load contents of Register Q into the Program Counter 0D  
PK   4   Save contents of the Program Counter in the Stack register, then load the contents of Register Q into the Program Counter 0C  
F8 Secondary memory reference (scratchpad) opcodes
AS r 1   Add contents of specified register to contents of Accumulator. increment or decrement ISAR if specified by r 1100aaaa  
ASD r 2   Add as BCD contents of specified register to contents of Accumulator. increment or decrement ISAR if specified by r 1101aaaa  
NS r 1   Logical AND contents of specified register to contents of Accumulator. increment or decrement ISAR if specified by r 1111aaaa  
XS r 1   Logical XOR contents of specified register to contents of Accumulator. increment or decrement ISAR if specified by r 1110aaaa  
DS r 1.5   Decrement (by one) specified register. increment or decrement ISAR if specified by r 0011aaaa  
AM   2.5   Add Accumulator contents to the contents of the memory location addressed by DC0. Increment DC0 88  
AMD   2.5   Decimal (BCD) add Accumulator contents to the contents of the memory location addressed by DC0. Increment DC0 89  
NM   2.5   Logical AND Accumulator contents with the contents of the memory location addressed by DC0. Increment DC0 8A  
OM   2.5   Logical OR Accumulator contents with the contents of the memory location addressed by DC0. Increment DC0 8B  
XM   2.5   Logical XOR Accumulator contents with the contents of the memory location addressed by DC0. Increment DC0 8C  
CM   2.5   Subtract the contents of Accumulator from contents of memory location addressed by DC0. Only the status flags are affected. Increment DC0. 8D  
F8 Immediate opcodes
LISU DATA3 1   Load immediate into the upper 3 bits of ISAR 01100ddd  
LISL DATA3 1   Load immediate into the lower 3 bits of ISAR 01101ddd  
DCI ADDR 6   Load immediate data into the DC0 2A QQQQ
LIS DATA4 1   Load immediate data into the lower four bits of Accumulator and clear upper four Accumulator bits 0111dddd  
LI DATA8 2.5   Load immediate data into Accumulator 20 YY
AI DATA8 2.5   Add immediate to Accumulator 24 YY
NI DATA8 2.5   Logical AND immediate to Accumulator 21 YY
OI DATA8 2.5   Logical OR immediate to Accumulator 22 YY
XI DATA8 2.5   Logical XOR immediate to Accumulator 23 YY
CI DATA8 2.5   Compare Immediate. subtract Accumulator contents from immediate data. Only the status flags are affected. 25 YY
F8 jump opcodes
PI ADDR 6.5   Save Program Counter in Stack register. Load immediate address into Program Counter 28 QQQQ
BR DISP 3.5   Add immediate displacement to contents of Program Counter 90 RR
JMP ADDR 5.5   Load immediate address into Program Counter. Load high order byte of address into Accumulator 29 QQQQ
F8 conditional branch opcode
BT DATA3,DISP 3 3.5 Logical OR 3 immediate bits with current TMASK. If any bit=0, add displacement to PC0 10000ddd RR
BF DATA4,DISP 3 3.5 If 4 immediate bits=FMASK, add displacement to PC0 1001dddd RR
BP DISP 3 3.5 Branch relative if sign bit = 1. 81 RR
BC DISP 3 3.5 Branch relative if carry bit = 1. 82 RR
BZ DISP 3 3.5 Branch relative if zero bit = 1. 84 RR
BM DISP 3 3.5 Branch relative if sign bit = 0. 91 RR
BNC DISP 3 3.5 Branch relative if carry bit = 0. 92 RR
BNZ DISP 3 3.5 Branch relative if zero bit = 0. 94 RR
BNO DISP 3 3.5 Branch relative if overflow bit = 0. 98 RR
BR7 DISP 3 3.5 Branch relative if three low bits of ISAR not = 111. 8F RR
F8 register to register move opcodes
XDC   2   Exchange the contents of DC0 and DC1 2C  
LR A,IS 1   Load the contents of ISAR into the Accumulator 0A  
LR IS,A 1   Load the contents of the Accumulator into ISAR 0B  
POP   2   Load contents of stack register into the Program Counter 1C  
F8 register to register operate opcode
ADC   2.5   Add contents of DC0 to Accumulator, which is treated as a signed binary number. Store the result in DC0 8E  
F8 register operate opcode
SR 1 1   Accumulator shift right. most significant bit is 0 12  
SR 4 1   Accumulator shift right by 4 bits. most significant 4 bits = 0000 14  
SL 1 1   Accumulator shift left. least significant bit is 0 13  
SL 4 1   Accumulator shift left by 4 bits. least significant 4 bits = 0000 15  
COM   1   Complement Accumulator contents. 18  
LNK   1   Add the carry to the contents of Accumulator. 19  
INC   1   Increment the contents of Accumulator. 1F  
CLR   1   Clear the contents of Accumulator. 70  
F8 interrupt opcodes
DI   2   Set interrupt enable bit in the Status register, W = 0 1A  
EI   2   Set interrupt enable bit in the Status register, W = 1 1B  
F8 status register opcodes
LR W,J 2   Move the contents of Scratchpad register 9 into the status register W. 1D  
LR J,W 1   Move the contents of status register W into the Scratchpad register 9. 1E  
F8 misc opcode
NOP   1   No Operation - A.K.A cycle waster 2B  

Colophon

Disclaimer: This document in no way represents Nyx. All opinions and errors are mine alone.
lowell.turner@ieee.org