Intel MCS-48 Information Page - pin outs, etc.

This page contains pin out information on Intel's MCS-48 system. The microprocessors in this system include:

The 8748H, 8749H, (EPROM devices)

The 8048AH, 8049AH, 8050AH (ROM devices)

And the 8035AHL, 8039AHL, 8040AHL CPU only devices.

[pin diagram of MCS-48 chips] MCS-48 pin diagram.

All of the devices share this pin diagram. However, Because of implementation differences, the uses may not be same. A description follows.

MCS-48 device differences
Device Internal - ROM Memory - RAM RAM standby
8050AH 4K x 8 256 x 8 yes
8049AH 2K x 8 128 x 8 yes
8048AH 1K x 8 64 x 8 yes
8040AHL none 256 x 8 yes
8039AHL none 128 x 8 yes
8035AHL none 64 x 8 yes
8749H 2K x 8 EPROM 128 x 8 no
8748H 1K x 8 EPROM 64 x 8 no

note that the 8749 and 8748 have EPROMs while the 8035, 8039 and 8040 have no internal ROM. Pay close attention to the following table. It shows the pin function differences for the various processors.
MCS-48 Pin Descriptions (*=active low signal)
Symbol Pin # Function Device
GND 20 Circuit Ground Potential all
Vdd 26 +5V during normal operation all
Low power standby pin 8048AH
Programming power supply (+21V). 8748H
Vcc 40 Main power supply; +5V during operation and programming all
PROG 25 Output strobe for 8243 I/O expander all
Program pulse (+18V) input pin During programming 8748H
Port 1
27-34 8-bit quasi-bidirectional port all
Port 2
8-bit quasi-bidirectional port. P20-P23 contain the four high order program counter bits during an external program memory fetch and serves as a 4-bit I/O expander bus for 8243 all
12-19 True bidirectional port which can be written or read synchronously using the RD*, WR* strobes. The port can also be statically latched. Contains the 8 low order program counter bits during an external program memory fetch, and receives the addressed instruction under the control of PSEN*. Also contains the address and data during an external RAM data store instruction, under control of ALE, RD*, and WR*. all
T0 1 Input pin testable using the conditional transfer instruction JT0 and JNT0. T0 can be designated as a clock output using ENT0 CLK instruction. all
Used during programming 8748H
T1 39 Input pin testable using the JT1, and JNT1 instructions. Can be designated the timer/counter input using the STRT CNT instruction. all
INT* 6 Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled after a reset. Also testable with conditional jump instruction. (Active low) interrupt must be held low for at least three machine cycles for proper operation. all
RD* 8 Output strobe activated during a BUS read. Can be used to enable data onto the bus from an external device. Used as a read strobe to external data memory. (Active low) all
RESET* 4 Input which is used to initialize the processor. (Active low) (Non TTL Vih) all
Used during power down. 8048AH
Used during programming. 8748H
Used during ROM verification. 8048AH
WR* 10 Output strobe during a bus write. (Active low) Used as write strobe to external data memory. all
ALE 11 Address latch enable. This signal occurs once during each cycle and is useful as a clock output. The negative edge of ALE strobes address into external data and program memory. all
PSEN* 9 Program store enable. This output occurs only during a fetch to external program memory. (Active low) all
SS* 5 Single step input can be used in conjunction with ALE to "single step" the processor through each instruction. all
Used in sync mode. 8048AH
EA 7 External access input which forces all program memory fetches to reference external memory. Useful for emulation and debug (Active high) all
Used during (18V) programming 8748H
Used during ROM verification (12V) 8048AH
XTAL1 2 One side of crystal input for internal oscillator. Also input for external source. (Non TTL Vih) all
XTAL2 3 Other side of crystal input. all

pin seven (EA) is of particular interest to hobbyists. For the ROM/EPROM units, tying pin seven high allows you to bypass the ROM/EPROM space and use only external memory.

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Disclaimer: This document in no way represents Nyx. All opinions and errors are mine alone.